1. Field of Invention
The present invention relates to a semiconductor structure and a fabricating method thereof. More particularly, the present invention relates to a semiconductor structure and a fabricating method thereof, which prevents the chip from cracking.
2. Description of Related Art
The integrate circuit (IC) devices have almost been applied everywhere along with the quick developments of the semiconductor manufacture. However, the fabrication processes of integrate circuit devices are very complicated, basically including four main stages: integrate circuit design, wafer fabrication, wafer testing and wafer packaging. In general, about hundreds of different process steps are required for the fabrication of the IC devices and the whole procedure may need one or two months to complete.
In order to achieve mass production and cost reduction, the diameter of the wafer has been evolved to 12 inches from the early 4 inches or 5 inches. Accordingly, more clips can be made simultaneously on one wafer. In the process of fabricating integrate circuits, many patterns for inspection or testing are generally formed on the scribe lines of the wafer. The patterns include, for example, alignment marks, inspecting/measuring patterns, testing patterns for electrical properties and product codes, etc. However, during the packaging processes, the wafer will be sliced into chips through cutting the scribe lines of the wafer.
Usually, there are a plurality of parallel horizontal scribe lines and a plurality of parallel vertical scribe lines in one silicon wafer. After the devices on the wafer are completed, the wafer is sliced by scribing along the scribe line on the wafer using a diamond blade to obtain a plurality of chips. Since material layers of different materials are formed covering the wafer, the material layers disposed on the scribe line may be damaged or cracked when the wafer is scribed.
Particularly, the above damages are near the corners of the chip. That is, the damages at the crosses of the scribe lines are the most serious because the stress focuses on the crosses of the scribe lines. Moreover, even after packaging, the external influences, i.e., the temperature changes, may result in the extension of cracks or delamination. Usually, delamination is likely to occur in the interfaces of the low-k dielectric material layer and other layers. It is because the adhesion between the low-k dielectric material layer and other dielectric layers or metal layers is usually not good. Accordingly, the performance of the device may be degraded or the lifetime may be reduced, thus increasing the costs of packaging processes and lowering the reliability of devices.